1. Field of the Invention
The present invention relates to semiconductor devices, and in particular, to a semiconductor device including hierarchically structured word lines.
2. Description of Prior Art
A semiconductor memory device represented by a DRAM (Dynamic Random Access Memory) generally includes hierarchically structured main word lines and sub-word lines. The main word line is a word line positioned at an upper hierarchy, and is selected by an upper bit of a row address. The sub-word line is a word line positioned at a lower hierarchy, and is selected based on a corresponding main word line and a word driver selecting line selected by a lower bit of the row address (Japanese Patent Application Laid Open No. 2012-243341).
A memory cell array such as the DRAM is generally divided into a plurality of memory mats to reduce the wiring capacity of the sub-word line and the bit line. The memory mat refers to an extending range of the sub-word line and the bit line. The main word line described above is assigned in plurals to one memory mat, so that when the main word line is selected using the upper bit of the row address, the memory mat to be selected is also determined at the same time.
The selection of the word driver selecting line, in principle, merely uses only the lower bit of the row address. Actually, however, not only the lower bit of the row address, but a part of the upper bit of the row address is also used. This is because if only the lower bit of the row address is used, one word driver selecting line needs to be made common with respect to all the memory mats, in which case, the wiring capacity becomes very large and thus is not realistic.
Actually, the word driver selecting line is divided, and one word driver selecting line is commonly assigned to multiple (e.g., two) memory mats to reduce the wiring capacity. Thus, not only is the lower bit of the row address used, but information for specifying the memory mat, for example, a part of the upper bits of the row address is also used for the selection of the word driver selecting line.
However, if the number of hits of the upper bits of the row address used for the selection of the word driver selecting line is large, the logic for selecting the word driver selecting line becomes complex and the circuit scale increases. Such problems are particularly significant when the number of memory mats cannot be expressed by power of two.